Supercomputing for the Future, Supercomputing from the Past.
Tuesday, May 12, 2009
9:00 am-10:00 am. Salmiah Room.
Abstract
Supercomputing is a zero billion dollar market but a huge driving boost for technology and systems for the future. Today, applications in the engineering and scientific world are the major users of the huge computational power offered by supercomputers. In the future, the commercial and business applications will increasingly have such high computational demands.
Supercomputers, once built on technology developed from scratch have now evolved towards the integration of commodity components. Designers of high end systems for the future have to closely monitor the evolution of mass marked developments. Such trends also imply that supercomputers themselves provide requirements for the performance and design of those components.
The current technology integration capability is actually allowing for the use of in other times supercomputing technologies within a single chip that will be used in all markets. Stressing the high end systems design will thus help develop ideas and techniques that will spread everywhere.
A general observation about supercomputers in the past is their relatively static operation (job allocation, interconnect routing, domain decompositions, loop scheduling) and often little much coordination between levels.
Flexibility and dynamicity are some key ideas that will have to be further stressed in the design of future supercomputers. The ability to accept and deal with variance (rather than stubbornly trying to eliminate it) will be important. Such variance may arise from the actual manufacturing/operation mode of the different components (chip layout, MPI internals, and contention for shared resources such as memory or interconnect...) or the more and more dynamic nature of the applications themselves. Such variability will be perceived as load imbalance by an actual run. Properly addressing this issue will be very important.
The application behavior typically shows repetitive patterns of resource usage. Even if such patterns may be dynamic, very often the timescales of such variability allows for the application of prediction techniques and matching resources to actual demands. Our foreseen systems will thus have dynamic mechanisms to support fine grain load balancing, while the policies will be applied at a coarse granularity.
As we approach fundamental limits in single processor design especially in terms of the performance/power ratio, multicore chips and massive parallelism will become necessary to achieve the required performance levels. A hierarchical structure is one of the unavoidable approaches to future systems design. Hierarchies will show up at all levels from processor to node and system design, both in the hardware and in the software.
The development of programming models (extending current ones or developing new ones) faces a challenge of providing the mechanism to express a certain level of hierarchy (but not too much/detailed) that can be matched by compilers, run times and OSs to the potentially very different underlying architectures. Programmability and portability of the programs (both functional and performance wise, both forward and backwards) is a key challenge for these systems.
The approach to address a massively parallel and hierarchical system with load balancing issues will require coordination between different scheduling/resource allocation policies and a tight integration of the design of the components at all levels: processor, interconnect, run time, programming model, applications, OS scheduler storage and Job scheduler.
By approaching the way of operation between supercomputers and general purpose, this zero billion dollar market can play a very important role of future unified-computing.
Bio
Mateo Valero, http://personals.ac.upc.edu/mateo/, obtained his PhD from UPC in 1980. He is a professor in the Computer Architecture Department at UPC. His research interests focuses on high performance architectures. He has published approximately 500 papers on these topics. He is the director of the Barcelona Supercomputing Center, the National Center of Supercomputing in Spain.
Dr. Valero has been honored with several awards. Among them, the Eckert-Mauchly Award the most important worldwide award in the field of Computer Architecture, received in 2007, by the IEEE, Institute of Electrical and Electronics Engineers and the ACM, the Association for Computing Machinery, two Spanish National awards, the "Julio Rey Pastor" in 2001, to recognize research on IT technologies, and the “Leonardo Torres Quevedo” in 2006, to recognize research in Engineering, by the Spanish Ministry of Science and Technology, presented by the King of Spain. In 1997, he received “the King Jaime I” in research by the Generalitat Valenciana and presented by the Queen of Spain, and In April
2008 he was awarded the “Aragon Award” by the Government of Aragon and he has also been named Honorary Doctor by the University of Chalmers and by the University of Belgrade.
In December 1994, Professor Valero became a founding member of the Royal Spanish Academy of Engineering. In 2005 he was elected /Correspondent Academic/ of the Spanish Royal Academy of Science and in 2006 and member of the Royal Spanish Academy of Doctors. In 2000 he became a Fellow of the IEEE. In 2002, he became an Intel Distinguished Research Fellow and a Fellow of the ACM, the Association for Computing Machinery. In 1998 he won a “Favorite Son” Award of his home town, Alfamén (Zaragoza)/ /and in 2006, his native town of Alfamén named their Public College.
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